Flash memory has recently been popular in embedded applications due to its non-volatility, quick access speed, shock resilience, and low power consumption. NAND flash memory plays a significant role in edge computing by providing non-volatile storage for edge devices. Modern handheld electronic devices use NAND flash memory as the primary data storage, and this trend is continuing in data centers. Reading/Writing with the memory requires a controller that communicates with the memory. This work presents the architectural development and hardware implementations of a memory interface controller for a NAND flash memory device. Hardware implementations are carried out on the Zynq UltraScale+ ZCU102 platform containing the xczu9eg-2ffvb1156-2-e FPGA device, and area/delay calculations are performed using an observable method. The implementation results are also provided with the UMC 28 nm CMOS ASIC. The contributions of this work lie in the development of the controller architecture, its hardware implementations, and the evaluation of its performance on different platforms.