In this paper an approximate adder is presented. This adder named as Accuracy Reconfigurable Carry Bypass Approximate Adder (ARCBAA) is an accuracy configurable adder (ACA) which aims to introduce different levels of approximations to a carry bypass adder (CBA). The reconfigurable nature of this adder allows it to operate in both accurate as well as approximate mode, making it suitable for error intolerant as well as error tolerant applications. Further, the availability of approximation level allows the adder to be configured to various application which may be tolerant to different amounts of error. To validate the performance of this adder, it has been synthesized using 180 nm osu018 open source standard cell library and benchmarked with state of the art approximate adders. The simulation results show that ARCBAA achieves over 23% reduction in area and about 49% improvement in the average error rate. It is observed that the proposed adder provides an improvement in average error of about 79% and a delay reduction of about 5.5% over the existing approximate adder. Finally, this adder has been integrated as a co-processor to the Rocketchip RISC-V SoC generator and evaluated using an image smoothening algorithm to study the advantages observed using this configuration.

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Accuracy Reconfigurable Carry Bypass Approximate Adder as Co-processor to RISC-V

  • Akhilesh Sreedharan,
  • Chetan Vudadha

摘要

In this paper an approximate adder is presented. This adder named as Accuracy Reconfigurable Carry Bypass Approximate Adder (ARCBAA) is an accuracy configurable adder (ACA) which aims to introduce different levels of approximations to a carry bypass adder (CBA). The reconfigurable nature of this adder allows it to operate in both accurate as well as approximate mode, making it suitable for error intolerant as well as error tolerant applications. Further, the availability of approximation level allows the adder to be configured to various application which may be tolerant to different amounts of error. To validate the performance of this adder, it has been synthesized using 180 nm osu018 open source standard cell library and benchmarked with state of the art approximate adders. The simulation results show that ARCBAA achieves over 23% reduction in area and about 49% improvement in the average error rate. It is observed that the proposed adder provides an improvement in average error of about 79% and a delay reduction of about 5.5% over the existing approximate adder. Finally, this adder has been integrated as a co-processor to the Rocketchip RISC-V SoC generator and evaluated using an image smoothening algorithm to study the advantages observed using this configuration.