In recent days, Authenticated Encryption has become predominant to emphasize the security of data between interconnected devices. ASCON is one of the lightweight authenticated encryption algorithms recommended by NIST. Two iterative architectures contributing toward high throughput and an iterative architecture focused toward low cost are proposed and implemented in both the FPGA and ASIC platforms. Algebraic Normal Form Boolean expressions are preferred to implement the compact version of the 5-bit S-box of ASCON. High throughput of 1002.36 Mbps is achieved for the design with a double permutation function per clock cycle in the Virtex-4 FPGA device. A minimum of 7891 Gate Equivalent area is sufficient for the proposed ASCON-128 architecture with a single permutation function per clock cycle in the ASIC platform. The proposed designs are suitable for IoT applications requiring high throughput and minimum area constraints.