Scholarlink

In analog and custom IC layout designing space, the pins (and resulting net shapes) are drawn as per DRC rules and the designers should also have considered the current-carrying requirements of the net and sized the pins accordingly for mature as well in advanced node designs. Layout designers cannot manually look at simulation results for each net/pin and resize the pins to meet current requirements. Electrical aware pin resizer and splitter has been developed which helps designers to find and resize pins automatically based on the current requirements, saving time, and increasing productivity by avoiding multiple iterations of electrical checks. This work enables the designers to increase their productivity tremendously.

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Reducing Layout Design Cycle Iterations by Resizing and Splitting Electrically Violated Pins by Push Button

  • 会议论文

  • 发表日期：

    2025年

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  • Neha Agrawal,
  • Garima Batra,
  • Abhishek Kumar,
  • Hitesh Marwah

摘要

In analog and custom IC layout designing space, the pins (and resulting net shapes) are drawn as per DRC rules and the designers should also have considered the current-carrying requirements of the net and sized the pins accordingly for mature as well in advanced node designs. Layout designers cannot manually look at simulation results for each net/pin and resize the pins to meet current requirements. Electrical aware pin resizer and splitter has been developed which helps designers to find and resize pins automatically based on the current requirements, saving time, and increasing productivity by avoiding multiple iterations of electrical checks. This work enables the designers to increase their productivity tremendously.