This paper describes design and development of SPARC processor-based Radar controller (SPRC) Application Specific Integrated Circuit (ASIC), which has been developed for ISRO’s various Microwave Synthetic Aperture Radar (SAR) missions. SPRC ASIC is used in RADAR Controller (RC) subsystem design which command and control the Radar operation. The SPRC ASIC is based on 32-bit SPARC V8 compliant processor with a 32-bit IEEE-754 compliant Floating-Point Co-processor (FPC). The FPC is used for real-time computation of SAR Operational Configuration (SOC) parameters based on the stored Digital Elevation Model (DEM). SPRC ASIC has on-chip MIL-STD-1553 RT IP core, TSRG, SPI, UART, and GPIO modules. MIL-STD-1553 RT IP core configures RC as a Remote Terminal (RT) of MIL-STD-1553 interface where Spacecraft Bus Management Unit (BMU) acts as a Bus Controller (BC). Timing Signal Regenerator (TSRG) module contains array of programmable pulse generators which generate timing signal for Radar operation. SPI is used to configure other payload subsystems. There are two Universal Asynchronous Receiver Transmitter (UART) modules for serial communication. GPIOs are used for control and command operation of other subsystems. SPRC ASIC has on-chip 512-KB SPRAM and 32-KB DPRAM for various applications. SPRC ASIC has been realized on 180 nm CMOS process of Semiconductor Laboratory (SCL), India, with 160-pin CQFP package. It operates at 75 MHz and dissipates less than 1 W. This paper describes the need, concept, architecture, and design methodology of SPARC processor-based Radar controller (SPRC) for Microwave Remote Sensing Payloads.