RISC-V processors based on increasingly popular open standard instruction set architecture (ISA) are challenging to verify because of their optional features, implementation flexibility, and custom extensions. However, their uniformity and modular design present a unique opportunity to develop a high-quality verification environment automatically. In this paper, we propose a tool named Codriver, which automatically produces a test environment for RISC-V processors using constrained random test vector generation, followed by an intelligent feedback mechanism. The results on four different RISC-V ISAs demonstrate Codriver’s capabilities, effectiveness, and versatility. The feedback mechanism applies incremental patches to the test bench to fill the functional coverage gaps and achieves high coverage ( \(\sim 99\%\) ) with a small set of instructions ( \(\sim 300-400\) ).