Approximate computing has emerged as a potent technique to reduce area overhead and computational delay, albeit at the cost of a limited loss in result precision. Consequently, numerous approximate versions of accurate adder and multiplier designs utilizing approximate computing techniques have been explored in the literature. However, since these designs are often derived from a single accurate design, they inherit the drawbacks and hardware-level inefficiencies of their accurate counterparts. In this paper, we propose a hybrid approximate adder, ‘HyAdd’ that relies on computing different sections of the input operands via different adder designs. HyAdd divides the overall computation into three segments and then performs the addition operation using indifferent techniques in a non-blocking parallel manner. To validate the efficacy of the proposed design, we have evaluated it across real-time applications and analyzed the results in contrast to existing designs. Our evaluation results demonstrate that the proposed adder design produces results that are 22.48% more accurate than the existing state-of-the-art adders. Additionally, the proposed design provides an energy savings of 24.67% when compared to existing adder designs.