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A chip designer mainly focuses on reducing area, power consumption, and delay when designing Integrated Circuit (IC). In many Digital Signal Processing (DSP) systems, multipliers play a vital role. If the delay of multipliers gets reduced, it will change the whole circuit delay, so researchers are going to reduce the area and delay of the circuit. This paper basically gives information about the comparison of all types of parallel multipliers such as an array, Baugh-Wooley, braun, and a tree multiplier that is the daddamultiplieronultra-scale Field Programmable Gate Array (FPGA) devices. Which gives analysis about the capability and performance of multipliers. This simulation work is done on the Xilinx using the ISM simulator, different ultrascale FPGA devices (Znyque, Kintex 7, Virtex 7, and Artix 7). In the last, a comparative table gives information about the different parameters like delay and area (Number of Look-up tables) used by the particular multiplier. The abstract should summarize the contents of the paper in short terms, i.e. 150–250 words.

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Delay Assessment of Parallel Multiplier Using Ultra-Scale FPGA Devices

  • 会议论文

  • 发表日期：

    2025年

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  • Shivangi Awasthi,
  • Chandrasekhar Aditya,
  • Parveen Kumar,
  • Balwinder Singh

摘要

A chip designer mainly focuses on reducing area, power consumption, and delay when designing Integrated Circuit (IC). In many Digital Signal Processing (DSP) systems, multipliers play a vital role. If the delay of multipliers gets reduced, it will change the whole circuit delay, so researchers are going to reduce the area and delay of the circuit. This paper basically gives information about the comparison of all types of parallel multipliers such as an array, Baugh-Wooley, braun, and a tree multiplier that is the daddamultiplieronultra-scale Field Programmable Gate Array (FPGA) devices. Which gives analysis about the capability and performance of multipliers. This simulation work is done on the Xilinx using the ISM simulator, different ultrascale FPGA devices (Znyque, Kintex 7, Virtex 7, and Artix 7). In the last, a comparative table gives information about the different parameters like delay and area (Number of Look-up tables) used by the particular multiplier. The abstract should summarize the contents of the paper in short terms, i.e. 150–250 words.