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In-memory computing (IMC) is a cutting-edge technology that has disrupted the conventional approach of computing, instead of data is stored separately and processed, in-memory computing eliminates delays, reduces energy consumption, and minimizes resource wastage by addressing the memory bottleneck issue during computation. Leveraging the speed and efficiency of RAM (Random Access Memory), IMC offers fast data access and computation, making it ideal for handling large-scale data-intensive tasks and real-time analytics. This paper consists of design and simulation of 6T SRAM cell array and Multifunctional in memory computing logic circuit to implement the basic two input digital logic gates such as AND, NOR, NAND, OR, XOR and XNOR. Additionally same architecture can perform Half Adder operation and 2-bit binary to gray conversion. The proposed circuit is designed using PTM32nm (Predictive Technology Model) technology node with 1 V operating voltage and implemented in LTSpice Software. The circuit performs bitwise operations, enabling simultaneous read and perform each logic operation parallelly.

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Design and Implementation of Multifunctional Logic Circuits Using SRAM Cells Utilizing In-Memory Computing Concept

  • 会议论文

  • 发表日期：

    2025年

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  • Nazida Ansari,
  • Umayia Mushtaq,
  • Seema Eram,
  • Md. Waseem Akram

摘要

In-memory computing (IMC) is a cutting-edge technology that has disrupted the conventional approach of computing, instead of data is stored separately and processed, in-memory computing eliminates delays, reduces energy consumption, and minimizes resource wastage by addressing the memory bottleneck issue during computation. Leveraging the speed and efficiency of RAM (Random Access Memory), IMC offers fast data access and computation, making it ideal for handling large-scale data-intensive tasks and real-time analytics. This paper consists of design and simulation of 6T SRAM cell array and Multifunctional in memory computing logic circuit to implement the basic two input digital logic gates such as AND, NOR, NAND, OR, XOR and XNOR. Additionally same architecture can perform Half Adder operation and 2-bit binary to gray conversion. The proposed circuit is designed using PTM32nm (Predictive Technology Model) technology node with 1 V operating voltage and implemented in LTSpice Software. The circuit performs bitwise operations, enabling simultaneous read and perform each logic operation parallelly.