Silicon technologies advance at a quicker rate every year as the size of semiconductor devices reduces in response to the growing demand for high performance, such as higher operating frequency or faster-operating speed devices based on FETs and other transistors. There is a minimum of a single common substrate interface for every gate in a circuit that is digital. As a result, there will be a huge number of substrate interactions in the digital design. Consequently, the digital circuit achieves an extremely low impedance to the substrate surface throughout its area. A low impedance can be produced especially when the substrate comes in contact from the analog circuit to the ground, will result in substrate noise within the analog region. In order to solve this problem and prevent low impedance performance, the analog circuit needs to have a high enough PSRR. For PSSR, the capacitive coupling-based shielding technique is used. In this designed model, a 14 nm N-MOSFET is designed on SILVACO ATHENA with HfO2/WSi2 dielectric medium for evaluating the substrate noise in this designed model. Using the simulator, it’s possible to manually inject noise models such as Drain Current Noise, Poisson’s Equation (shot noise) and Energy Balance etc. Subsequently, the noise is reduced through the substrate noise coupling technique. Shielding is the most popular technique for reducing noise in capacitive coupling. For evaluating the performance of the model, the I-V characteristics, transfer characteristics and substrate noise evaluation are considered. The attained I-V characteristics, On/Off ratio and minimum noise figure values of the proposed model are 0.2 mA for 1.2 (Vd), 10-4-10-3 and 0–1.5. Thus, an excellent output of noise reduction is done by using capacitive coupling.