Design and Implementation of a Low-Power JESD204B Transmitter with Wideband Fractional-N Ring PLL in 40-Nm CMOS Process
摘要
This paper presents a transmitter circuit for high-speed data transmission in ADC applications, providing a wide frequency output range of 1–16 Gbps through parallel-to-serial conversion. A source-series-terminated (SST) transmitter achieves 1.2 Vpp output swing and incorporates a voltage regulator structure to mitigate power supply noise interference. The output frequency range is extended through the use of a two-stage differential ring oscillator and a sigma-delta fractional divider. Fabricated in 40-nm CMOS, the transmitter occupies an area of 0.074 mm2 and achieves an output frequency range of 1–16 Gbps while operating over channels with 13.5 dB loss at Nyquist, consuming 3.8 mW/Gb/s.