Dual-Edge Triggered Reset Synchronizer for I2C Protocol

In this paper, dual-edge triggered reset synchronizer for Inter Integrated Circuit (I2C) protocol is proposed. The proposed reset synchronizer design aims for the asynchronous reset to have asynchronous assertion and synchronous deassertion for I2C slave protocol, in which system reset and software reset is synchronized to a targeted clock. This is to avoid the metastability issue when the reset is released with respect to the target clock. Taking the role of I2C START condition, which signifies the beginning of a transmission, the proposed methodology uses START condition as a clock to synchronize the external reset or software reset before transmission begins. Both edges of the START signal will be used for synchronization. Since START timing must be respected according to I2C protocol, it is safe to be used as a clock without impacting any setup/hold (reset/recovery) timing issue.