Ternary D Flip-Flop in CNFET–Memristor Technology

A D flip-flop in ternary logic is presented in this paper, which is used to store a ternary digit using Carbon Nanotube FET (CNFET)–memristor technology. This paper presents three designs of the D flip-flop; one is a latch-based D flip-flop that is edge-triggered using a master-slave configuration, named LDFF. The other designs use a transmission gate and a buffer to design a D flip-flop with positive edge-triggering. Using a standard ternary inverter and ternary cycle operators, a ternary buffer is designed. A cycle operator-based ternary D flip-flop is named CDFF, which uses cycle operators in the loop to store a digit. A D flip-flop that is positive edge-triggered and designed using a standard ternary inverter is named SDFF, which has a smaller number of CNFETs and memristors. Out of these three designs, SDFF has a superior PDP in comparison to other designs. In particular, the SDFF takes 40 \(\%\) and 63 \(\%\) of energy compared to the LDFF and CDFF, respectively. We have extended the ternary D flip-flop to design a synchronous ternary counter. Extensive simulations were performed, and simulation plots were presented.