Design and Implementation of Parameterized Posit Adder and Arithmetic Logic Unit Using Adder-Based Leading One Detector

Posits provide better dynamic range and accuracy over IEEE-754 floating-point units. In this work, we proposed a parameterized posit adder for multiple posit formats (N, ES) and a single architecture to perform an Arithmetic Logic Unit (ALU) to perform the different posit operations such as addition, subtraction, multiplication, and Multiply and Accumulate (MAC). To perform any posit arithmetic operation, it is necessary to extract the bit fields to perform any posit arithmetic operations, so an additional circuitry is required to extract the bit fields. To extract the length of the regime bit field, we have proposed the usage of the adder-based leading one detector (LOD) instead of the existing multiplexer-based LOD. The adder-based LOD reduces the design’s area and critical path delay. Further, we have used lower order size adders to determine the final exponent and regime fields of the sum of the posit adder. To compare the proposed designs with the existing ones, we have considered the product of a number of lookup tables (LUTs) and propagation delay as \(\text {Area} \times \text {Delay}\) as one of the performance metrics. The synthesis results show that, with the proposed posit adder at (32, 2) posit format, we have reduced \(\text {Area} \times \text {delay}\) by 15.69% and 35.71% compared with existing works.