Thermo-electro-mechanical Effects of Copper TSV Interconnects on the MOS Characteristics in Stacked 3D Integration

Stacked 3 Dimensional IC (3DIC) is one of the profound potential structures for boosting the features and performances of the chip. The basic layout of it is having components like the substrate (Si), SiO2, metal for through Si via (TSV) and so on. These different types of used materials in a 3DIC develop a mismatch of the coefficient of thermal expansion (CTE). Simultaneously, during the circuit operation, there is simultaneous generation of heat in the substrate and in the surroundings of the 3DIC. Both the mismatch in CTE and generation of heat results in an expansion of the materials thereby inducing local stress. In this paper, we have analyzed the impact of TSV-aided stress on MOSFET characteristics generated by the stacked 3D structure. The variation of stress characteristics of a stacked 3DIC structure was studied by considering a simple device simulation method.