Preliminary Numerical Investigation of the Use of Chip Inductor for Eddy Current Testing

Numerical investigation of the feasibility of using a chip inductor as an eddy current (EC) probe is presented in this work. The electrical behavior of the chip inductor is modeled using finite element method (FEM)-based numerical simulation. Commercially available chip inductors were modeled in MAXWELL, Ansys simulation software and the permeability ( \({\mu }_{r}\) ) of the ferrite core and number of turns in the coil ( \(N\) ) were estimated using parametric sweeps. Numerical simulations were performed for shielded and unshielded chip inductors. EC testing (ECT) of a 10 mm thick Aluminum plate was investigated over 100–1000 kHz based on the material properties of the specimen and the electrical impedance of the chip inductor. Change in the electrical impedance of the shielded chip inductor was analyzed for a 2 mm wide axial defect in the 10 mm plate specimen with varying defect depths. Simulation results indicated reduction in mutual coupling for shielded chip inductor compared to the unshielded model. Numerical simulations suggest the feasibility of broadband excitation for the chip inductor due to the minimum parasitic effects. Based on the simulation study, it is concluded that shielded chip inductor could be used for designing low profile EC probes for non-destructive testing of thin metallic specimens.