Gigabit Ethernet TCP Hardware Stack Construction Based on FPGA

To realize high-speed and reliable transmission of navigation information data and processing results to other devices. This paper constructs TCP hardware protocol stack based on FPGA. According to the idea of hierarchical processing and modular design, the complex data transmission process is simplified into the process of data “encapsulation - cycle - unencapsulation”. The functions of address resolution protocol ARP, TCP connection establishment, data communication and disconnection are successfully implemented. Test the TCP transmission rate. When the data transfer is stable, the maximum speed can reach 379 Mb/s. It basically meets the network transmission requirements of satellite navigation equipment at the present stage. In addition, this paper also realizes the TCP/IP protocol in a pure logic way. If it can be integrated into the chip through the complete IC design verification, the prospect is incalculable.