Analysis of Multiply-Accumulate (MAC) Unit Using Convolution Neural Networks (CNN)

In digital signal processing (DSP) applications, the multiplicative accumulator (MAC) process serves as the primary cognitive kernel. The MAC unit, which is constantly on the critical route, determines the overall system speed. A high-speed MAC is a crucial step for real-time DSP applications. A system that requires the least amount of electricity will almost probably dominate the worldwide market because of the ongoing need for small, portable devices. As a result, the development of a MAC unit with low power consumption is essential. Scientists have made several attempts to develop MAC architecture with great computation efficiency and minimal power utilization. Convolutional neural networks (CNNs) are highly effective for image, voice, and video processing but they require a lot of processing power and memory bandwidth. To solve this, hardware accelerators with plenty of multiply-accumulate (MAC) units have been proposed. However, these units increase integrated circuit (IC) gate count and power consumption due to their large multipliers. Weight-sharing accelerators compress trained CNN weight values into bins, reducing gate count and power consumption. The parallel accumulator with hybrid adder structure presented in the model is modified to use an alternative technique that involves changing the MAC units to add up each weight’s frequency and grouping the results into bins. The actual value accumulation takes place during the working multiplication phase, which considerably reduces the CNN’s gate count and power consumption. The proposed approach leverages the advantages of Wallace tree-based arithmetic units and hybridizes them with other efficient hardware structures, resulting in a highly optimized architecture for CNN layers. By carefully balancing resource utilization and performance, this approach enables the acceleration of CNN layer computations while efficiently utilizing FPGA resources. Experimental results demonstrate that the hybrid Wallace tree approach achieves significant improvements in speed and resource efficiency compared to traditional FPGA-based CNN implementations, making it a promising solution for the deployment of CNNs in resource-constrained environments, such as edge devices and embedded systems.