In modern system-on-chips (SoCs), embedded static random access memory (SRAM) units are vital components that facilitate on-chip memory for fast data storage and access. However, traditional SRAM cells based on metal oxide semiconductor (MOS) designs consume relatively high power, making them less suitable for power-constrained devices. Researchers are tackling the constraints of SRAM technology by investigating refined approaches rooted in carbon nanotube field-effect transistors (CNTFETs) which includes fine-tuning of model Parameters like nanotube diameter, flat band voltage, and CNT density to enhance SRAM cell performance and efficiency and to create more advanced and power-efficient memory solutions. The objective of this work is to design, evaluate and predict the performance of different SRAM cell by incorporating low-power strategies within 5 nm node CNTFET 6 T SRAM cell. These strategies encompass the Sleepy approach, Header approach, Footer approach, Zigzag approach, Leakage feedback approach, Stack approach, Leakage feedback with stack approach, Sleepy keeper approach, Sleepy stack approach, and Sleepy stack with keeper approach. To evaluate their effectiveness, the research paper uses performance metrics such as noise margin, delay, and leakage power.