Effect of Channel Epilayer Thickness on Low Power Analog Operation of Asymmetric U-Shaped pTFET

This article demonstrates the impact of variation of thickness of vertical channel epilayer (Tepi) for an asymmetric U-shaped pTFET (AU-pTFET) device to find its suitability for low power analog operation. A set of performance metrics, viz., OFF-state leakage power, transconductance (gm), output resistance (rout), gain (gm × rout), has been extracted for the projected device with Tepi as a parameter. An in-depth analysis of the performance metrics reveals a gradual increase in gain (156 times improvement for 10-nm Tepi over 2-nm Tepi at VDS = VDD) as well as a reduction in leakage power (84.7% reduction for 10-nm Tepi over 2-nm Tepi at VDS = VDD) with the increase in the value of Tepi. While, on the other hand, device with smaller Tepi value, besides producing higher drive current, ensures smaller device footprint, leading to higher package density and hence system compactness.