Performance of Strained-SiGe in FinFETs and Stacked Nanosheet FETs for Sub-7 nm Technology Node

The dc performances of FinFETs and NSFETs considering the stress effects using fully-calibrated technology computer-aided design (TCAD) simulations are investigated. The impact of stress on the electrical performances of FinFET and stacked NSFET at sub-7 nm technology nodes are analyzed. It is found that the stacked NSFETs have larger compressive stress due to wider effective channel width which improves the carrier mobility. The simulation results predict that the stress effect strongly influences the stacked NSFET with 29% and 15% enhancement in the ION and VTH respectively and degradation in SS as compared to the FinFET. Overall, the NSFETs can provide versatile design options and higher intrinsic performance compared to FinFETs for future technology nodes.