Optimization of Negative Differential Conductance (NDC) Point for Multi Gate Devices Considering Self Heating Effects Using Surface to Volume Ratio (SVR)

For future Analog and RF SoCs (System on Chip) design, 14 nm SOI FinFET is the potential candidate due to its better SCE (Short Channel Effect) capability and higher current drive strength. The Channel region of FinFET is confined by low thermal conductivity HiK material which offers a weaker heat flow path than classical MOSFET. It causes the self-heating effect, which leads to higher lattice temperature. Beyond the negative Differential Conductance (NDC) point, ON current starts decreasing due to high lattice temperature. The NDC point is a critical design parameter for Analog and RF circuit applications since the output conductance is negative beyond this point. Lattice temperature is highly dependent on the Surface to Volume ratio of FinFET, and the NDC point is the function of lattice temperature. So, in this work, Electrothermal simulation was performed on experimentally calibrated 14 nm SOI FinFET using Synopsys TCAD. Variation of lattice temperature with aspect ratio at a different gate length, extension length and fin height is studied. We have analyzed and optimized the NDC point in 14 nm SOI FinFET using the Surface to Volume Ratio approach and provided the design guidelines for Analog and RF circuit design.