Performance Projection of Stacked Silicon Nanosheet-FET Architectures for Future Technology Node

Silicon-based gate all around nanosheet field-effect transistor (NS-FET) have been emerged as a promising candidate for 5 nm and beyond technology node as it offers superior gate control over the channel and excellent current drivability. Despite stacked nanosheet designs have been reported the excellent switching performance over Fin-FET at the 3 nm technology node, their performance at lower technology node is limited by carrier mobility degradation and layer parasitic capacitance. Therefore, this work examines and compares the emerging nanosheet stacking architectures, such as stacked, sub-stacked, and tree-type, for logic applications at 1 nm technology node. The performance analysis of NS-FET, is done using a fully calibrated three-dimensional (3-D) TCAD simulation, based on self-consistent solutions of 3-D Poisson’s equation and Boltzmann equation with correction terms for accounting the short channel device physics. The results show that, at 1 nm technology node, tree-FET architecture with three channels is a more favorable candidate over stacked and sub-stacked stacking architectures with higher ON current, lower device delay, and smaller power delay product. The tree-type nanosheet stacking architecture offers several performance benefits and is expected to be a promising architecture for future low-power digital applications.