Design of Low Power Booth Multiplier with Enhance Pre-logic Mechanism Using Verilog

A Booth Radix-4 multiplier is a commonly used digital circuit for performing high-speed multiplication of binary numbers in modern microprocessors. Low power consumption is a critical requirement for modern electronic devices and designing a low power Booth Radix-4 multiplier has become an important research area. This paper proposes a low-power Booth Radix-4 multiplier with improved design by using pre-logic to generate the enable signal (pre-encoder) that uses a new approach to reduce the power consumption by minimizing the switching activity in the circuit by disabling traditional booth encoder and decoder and thus prevent from reductant working. The proposed multiplier achieves a significant reduction in power consumption compared to existing Radix-4 Booth multipliers while maintaining high performance and accuracy. The research shows the improved power performance with respect to existing Radix-4 Booth multipliers while maintaining high performance and accuracy. The design is implemented using Verilog HDL and simulated using Xilinx Vivado 2020.2. Simulation results demonstrate that the total power is reduced by 5.082% while dynamic power, static power consumption is reduced by 3.002%, 71.298%, respectively, and whereas a significant reduction of LUT by 17.8082%