Implementing Power and Performance Optimization Techniques on Wireless SoC Design at Synthesis

The current trends in the VLSI sector are low-power and high-frequency designs. Technology is getting smaller, design complexity is rising, and leakage power has significantly increased as a factor in total power dissipation. Optimization is necessary for lowering power and area requirements and improving performance. It can be done at several stages of a design flow, including synthesis, floorplan, placement and route, and clock tree synthesis (CTS). This paper primarily focuses on methods that optimize the design in terms of power and performance at synthesis stage. The type of VT cells utilized in the experiments greatly affected power and performance of the design. It draws attention toward the techniques employed to accomplish PPA goals, including ungrouping, boundary optimization, and clock gating.