A Time Series Data Compression Co-processor Based on RISC-V Custom Instructions

With the widespread use of IoT devices, the issue of high data transaction pressure introduces a new set of challenges. To overcome the conflict of limited network resources and the growing requirement of transforming generated data from IoT devices, academia has attempted to bring compression algorithms into IoT devices. These research efforts have resulted in a series of compression algorithms for time series data. Meanwhile, with the research on the RISC-V instruction set, its custom instructions provide a platform for implementing DSA. In this thesis, we propose a set of custom extended instructions to compute the compression of time series float data based on the Nuclei open source RISC-V core Hummingbird E203, using the Nuclei Instruction Co-unit Extension (NICE) interface. The compression co-processor uses asynchronous memory access and is independent of the core’s main pipeline. Cores with the co-processor demonstrate over 95% acceleration compared to the software solution, achieving compression rates of around 3–10 when working on 32-bit float data with more than 10,000 input points. Furthermore, the implementation requires only a minimal amount of hardware resources.