Analysis of Clock Gating Techniques for Low Power

The authors present an analysis of various clock gating techniques and its power requirements considering an application. Whenever the number of transistors to be mounted on single chip enhances, need for power optimization increases in the same pace. In the design of SoC, the reduction of power plays a vital role. When considered in sequential design source of power consumption is dynamic power. The clock gating technique reduces this dynamic clock to larger extent. In this paper, authors have implemented various clock gating techniques on test circuit. Power analysis is carried out using X-power analyzer to study the power optimization. From experimental results, it is observed that autogated clock gating technique consumes 68.63% power when compared with design under test without clock gating technique.