Out-of-Order Execution of Instructions for In-Order Five-Stage RISC-V Processor

In recent years, there have been remarkable advancements in Integrated Circuit (IC) technology, enabling the development of highly sophisticated computer systems on a single chip. Custom System on Chip (SoC) designs, where the processor core(s) and cache represent a smaller portion of the overall chip, have gained widespread popularity. Nowadays, it is challenging to come across an electronic product of any size that does not incorporate a processor. Open-source instruction set architecture, such as RISC-V-based processors, has gained traction in custom SoC design. A processor is the core of an electronic system. In a five-stage pipelined RISC-V processor, instructions are executed in the sequence that they are given. In this work, the architecture suggests an out-of-order execution of instructions when the resources are available yet all instructions are to be blocked owing to a multi-cycle instruction. In this architecture, in comparison with an in-order execution, we notice a difference of 120 ns, i.e., six clock cycles being used efficiently in an out-of-order execution when a multi-cycle instruction is executed.