Design and Analysis of 10-nm FD-SOI FinFET by Dual-Dielectric Spacers for High-Speed Switching

Based on Moore’s law, the number of transistors is widely increasing on a chip as it leads to the formation of complex SoC design. Transistor nanotechnology will depend on the length of the channel between the source-drain terminals of a transistor. The proposed work depicts the design of Fully Depleted Silicon On Insulator FinFET with the channel doping concentration of 1 × 1019 cm−3 and the placing of dual-dielectric spacer combinations between source and drain terminals. The FinFETs are three-dimensional transistors built with certain characteristics and properties since by use of dielectric materials in the design will result in the reduction of leakage current and improve short-channel effects (SCEs). Hence, the designed FinFET performance is analyzed by using Visual TCAD tool.