Area and Energy Efficient Booth Radix-4 Signed Multiplier Using Verilog

Multiplication is one of the most important and most frequently used operation in many DSP computations. Multiplier is the basic operation in many VLSI circuits. Some of the DSP applications such as convolution, correlation etc., uses the multiplication very frequently in the any design. So their performance depends on the Multiplier and the Multiplier’s performance depends on the type of adders that we used to implement it because the multiplication operations are critical so we use the adders. Multipliers can be optimized in terms of the area, delay and power by diminishing the no. of partial products produced, by using a fast adder unit and by taking care of the implementing logic. The main objective is to design a signed 8-bit multiplier which is efficient in terms of area occupied and energy by using Booth Radix-4 Encoding Technique. By exploring the characteristics of the signed numbers, the design effectively minimizes the number of arithmetic operations required, resulting in reduced latency and improved energy efficiency. Furthermore, the architecture incorporates parallelism and pipelining to enable high throughput in the multiplier module. With the extensive simulations and comparisons with the existing designs demonstrates that the proposed multiplier achieves significant energy savings without sacrificing its performance. In this proposed work the partial products are generated in parallel to improve the performance and the adders used for the partial product addition that are implemented by using decoder logic.