Efficient Three-Operand Binary Adder with Ladner Fischer Architecture

The three-operand binary adder is an essential practical unit to carry out the modular mathematics in numerous cryptography algorithms. The Carry-save adder is mainly used to perform the three-operands addition; however, the propagation delay could be very excessive because of the ripple carry adder present in the carry-save adder. In Han-Carlson adder, the three-operand addition can be accomplished by adding the third operand to the result of the first two operands, but this requires extra hardware. So the area and delays both are simultaneously reduced by the proposed high-speed area-efficient three-operand binary adder. Both the parameters are optimized by replacing the Han-Carlson adder with the Ladner Fischer adder. The proposed architecture is synthesized and implemented with the Xilinx Vivado and Zynq-7000 FPGA family. The Virtual Input-Output (VIO) intellectual prototype concept is used to add three operands, each operand with 32-bit size. The proposed architecture is 1.66 times faster than the Han-Carlson adder with a reduced LUT count.