Stability Aware Low-Power 8 T SRAM Cell Using CNFET in 22 nm Technology

In today’s technological world, static random-access memory (SRAM) is one of the most important and vital memory devices. CMOS scaling is a continual process. The performance of a 6 T SRAM cell is severely limited by technology. In terms of stability and leakage power with only a slim likelihood of success in the future, enhanced MOSFET technology and carbon CNTFETs (nanotube field-effect transistors) are frequently used. As prospective alternatives, they have been looked into. The standard CMOS-based system is discussed in this work. 6 T SRAM cell and projected PD 8 T SRAM cell are compared with CNTFET-based SRAM cell. The Cadence Virtuoso is used to design both standard 6 T SRAM cells and PD 8 T SRAM cells. In 22 nm technology, there is a tool. The SRAM cell based on CNTFETs is technology agnostic. The performance of the CNTFET-based SRAM cell is tested in terms of leakage power, latency, and stability to prove that it can effectively replace the CMOS-based SRAM cell.