Electrical Performance Analysis of 20-nm Gate Length Based FinFET

An electrical performance characteristic of p-type lightly doped channel Silicon on Insulator (SOI) FinFET is performed. In this work, the gate and channel length is set at 20 nm and the material having high dielectric constant 25 hafnium dioxide (HfO2) is used for gate oxide layer. By changing gate length, the performance of various parameters are investigated such as threshold voltage, drain current, drain-induced-barrier-lowering (DIBL), ON/OFF current, current density, and recombination rate. The results showed that by hafnium dioxide and gradual decreases of gate length, the ON/OFF current increases which upsurges threshold voltage, thus the drain current is increased which gives better performance of the device. The DIBL and leakage current of the device are also decreased. The simulation result also gives the adverse behavior of device after declining gate length below 20 nm. Shortening of gate length loses its control over the channel and the negative drain current leakage occurs.