Energy Efficient VgSOT-MTJ Based 1 Bit Subtractor

To harness the potential of VgSOT MRAM in digital signal processing circuits, this study presents a 1-bit full subtraction circuit based on voltage gated Spin–Orbit Torque Magnetic Tunnel Junction (MTJ) technology. The circuit design adopts a dual-track structure that seamlessly integrates CMOS and MTJ components. By precisely controlling the timing of reading and writing operations, the circuit achieves the desired full subtraction functionality. This integrated structure enables the seamless integration of MTJ memory devices into the full subtractor circuit while significantly reducing overall power consumption by minimizing the frequency of MTJ writing operations. This paper has implemented VgSOT, SOT, and STT based subtractor and borrow circuit for performance evaluation. Performance parameters like average delay, energy consumption, and Average power consumption have been analyzed in this paper. With VgSOT MTJ based subtractor, performance improvement of 93% and 97% is seen in terms of energy/Average power consumption over SOT and STT based implementations. In terms of average delay. VgSOT MTJ based subtractor performs 47% and 69% better over SOT and STT based implementations.