An ultra-low power (ULP), write-assist static random-access memory (SRAM) is presented targeted for Internet of things (IoT) devices. The IoT application involves battery-enabled low standby power memory architecture in a subthreshold regime. Therefore, to improve standby power along with better cell stability at various process, voltage, and temperature (PVT) conditions, a process tolerant write assist 10 T SRAM (PTWA10T) is presented in this work. In addition, separate read and write path in proposed 10 T SRAM improves the static noise margins. This paper unveils a new SRAM design that boasts impressive gains in performance and efficiency compared to existing options. At a storage density of 8 kilobits, the proposed architecture slashes standby power consumption by 68.5 and 33% compared to conventional 6 T SRAM and read-decoupled 8 T SRAM designs, respectively. This is achieved while simultaneously boosting noise margins, with read static noise margin improving 8.5 times, write static noise margin a staggering 19 times better than traditional 6 T SRAM. These advancements pave the way for more energy-efficient and reliable memory systems in the future.