The intentional introduction of attacks on embedded systems, specifically advanced FPGAs and microcontrollers, is a common use for fault injection technique. The embedded system that is based on FPGA utilizes SRAM to store configuration data. Due to the advancement in technology and the increasing complexity of FPGA bit files, multiple-bit upset is becoming an important threat to FPGAs. Radiation threats in space environments also pose a threat to these devices. The purpose of this paper is to address these issues by proposing burst error modeling and a self-test hardware for fault injection (FISH). In the proposed fault injection architecture, multiple-bit upsets are injected on the design’s interconnect efficiently using FPGA without changing the value of flip-flops related to the design path. Since their values have not changed, it is not necessary to reload the same flops and memory with correct values. The proposed FISH architecture was evaluated using the Xilinx Zynq-7000 FPGA, and it performed two times faster than the existing techniques. The overhead for FPGA resource utilization is less than that of other existing designs, but it depends on how many fault injection points are used.