Scholarlink

The proliferation of battery-powered devices necessitates energy-efficient hardware design to maximize operational lifespan. Arithmetic Logic Units, while fundamental to computation, contribute significantly to power consumption in these devices. This paper proposed an ALU architecture designed to address this challenge. By integrating a Vedic multiplier, renowned for its computational efficiency, and implementing low-power design techniques for other core components, we achieve substantial improvements in both performance and energy efficiency. Our proposed design exhibits a remarkable 93.983% decline in power usage dissipation and 66.479% minimized delay in contrast to conventional ALU architectures. This work highlights the potential of Vedic mathematics and low-power design strategies for significantly extending the battery life of portable electronic devices.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

High-Performance Arithmetic Logic Unit (ALU) Based on Vedic Multiplier

  • 会议论文

  • 发表日期：

    2026年

查看全文
  • Lalit Kumar Dabi,
  • Kamlesh Kumar,
  • Manoj Kumar,
  • Priyanshu Lakra,
  • Mansi Jhamb

摘要

The proliferation of battery-powered devices necessitates energy-efficient hardware design to maximize operational lifespan. Arithmetic Logic Units, while fundamental to computation, contribute significantly to power consumption in these devices. This paper proposed an ALU architecture designed to address this challenge. By integrating a Vedic multiplier, renowned for its computational efficiency, and implementing low-power design techniques for other core components, we achieve substantial improvements in both performance and energy efficiency. Our proposed design exhibits a remarkable 93.983% decline in power usage dissipation and 66.479% minimized delay in contrast to conventional ALU architectures. This work highlights the potential of Vedic mathematics and low-power design strategies for significantly extending the battery life of portable electronic devices.