Processing-In-Memory (PIM) architectures reduce data movement, making them ideal for compute-intensive machine learning tasks. Static Random Access Memory (SRAM) is an ideal choice due to its mature design, compatibility with advanced processes, and ability to support high-performance computing. In FPGAs, Block Random Access Memory (BRAM) functions as an SRAM array, supporting highly parallel PIM architecture but facing challenges with intra-cell data movement during bit-serial computations. To address this, we propose a multi-BRAM FPGA-based PIM architecture with an optimized reduction interface that minimizes LUT use, reduces routing overhead, and achieves logarithmic latency scaling. We validate the proposed architecture on the Intel Arria 10 FPGA and evaluate the latency and resource usage of different reduction methods using a matrix-vector multiplication application. The results show that the proposed design achieves an excellent latency-resource trade-off compared to state-of-the-art FPGA-based PIM architectures: Depending on the selected state-of-the-art baseline, our proposed architecture achieves up to a 94.4% reduction in LUT utilization or an order-of-magnitude improvement in latency.