The tremendous growth and advances in high-speed communication systems have made the demand very high for low-power and high-speed applications for signal processing. To improve the performance and overall quality of digital signal processing (DSP) systems, there is an ultimate requirement for the high-speed multiplier and accumulator circuit (MAC). The speed and power of DSP systems are governed by MAC blocks. To reach toward the low-power consumption, we need the block enabling technique for MAC. This paper does the research for various MAC architectures, power consumption minimization technologies and designs a 4 × 4 multiplier and accumulator circuit.