The manuscript explores the DC performance of a novel negative capacitance source pocket double-gate tunnel FET (NC-SP-DGTFET) with an optimized negative capacitance source pocket across varying device dimensions. Key findings indicate that decreasing the channel length ( \(L_{ch}\) ) (30 nm–20 nm) increases both on current and subthreshold swing (SS). Conversely, increasing the source pocket length (L \(_\text {p}\) ) (2 nm–6 nm) and its doping concentration ( \(1\times 10^{18} \textrm{cm}^{-3}\) to \(2\times 10^{19} \textrm{cm}^{-3}\) ) enhances the on current while reducing SS. Furthermore, reducing the silicon thickness ( \(T_{si}\) ) decreases the off current. These results highlight the device’s potential suitability for high-speed applications.