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The full adder’s minimization is bolstered by its immense and assured application, resulting in high-end performance. The design engineer has the ability to uncover a variety of digital circuits that would not be facile to implement without the use of a full adder. This paper introduces a novel hybrid technique for the development of full adder (FA) that is reliant on INput Dependent Inverter Domino (INDIDO) logic integrated with Double-Gate MOSFET (DG-MOSFET). This proposed DG-MOSFET FA-based INDIDO Buffer (DG-IndiMFA) is evaluated for several design aspects including propagation delay (Td), power consumption (PWR), power delay product (PDP), energy delay product (EDP), and noise margin. The HSPICE software was used to simulate the circuit at a voltage supply of 0.7 V and at 16 nm technology node. Further, comparative analysis was done by comparing proposed with the existing FA at varied supply voltages at 16 nm. The proposed design demonstrates a significantly low PWR of 0.893 nW (6.11×), an improved Td of 0.085 ps (117,638.23×), a substantial PDP of 0.075 zJ, and an EDP of 0.006 zJ-ns which is further validated by the comprehensive robust analysis at 0.7 V. In addition, 4-Bit Ripple Carry Adder (4-DG-IndiM RCA) application circuit using the proposed DG-IndiMFA circuit is preferred and is investigated for design parameters at 16 nm at a supply voltage of 0.7 V. Enhanced results validate the physical layout design, as the proposed DG-IndiMFA circuit and proposed application 4-DG-IndiM RCA circuit occupy an optimized area of 20.6 µm2 and 90 µm2, respectively.

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High-Performance Neoteric DG-IndiMFA Design and Analysis Using INDIDO Buffer at 16 nm

  • 会议论文

  • 发表日期：

    2025年

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  • Ramsha Suhail,
  • Pragya Srivastava,
  • Richa Yadav,
  • Mahak Sahu,
  • Anushka Chourey

摘要

The full adder’s minimization is bolstered by its immense and assured application, resulting in high-end performance. The design engineer has the ability to uncover a variety of digital circuits that would not be facile to implement without the use of a full adder. This paper introduces a novel hybrid technique for the development of full adder (FA) that is reliant on INput Dependent Inverter Domino (INDIDO) logic integrated with Double-Gate MOSFET (DG-MOSFET). This proposed DG-MOSFET FA-based INDIDO Buffer (DG-IndiMFA) is evaluated for several design aspects including propagation delay (Td), power consumption (PWR), power delay product (PDP), energy delay product (EDP), and noise margin. The HSPICE software was used to simulate the circuit at a voltage supply of 0.7 V and at 16 nm technology node. Further, comparative analysis was done by comparing proposed with the existing FA at varied supply voltages at 16 nm. The proposed design demonstrates a significantly low PWR of 0.893 nW (6.11×), an improved Td of 0.085 ps (117,638.23×), a substantial PDP of 0.075 zJ, and an EDP of 0.006 zJ-ns which is further validated by the comprehensive robust analysis at 0.7 V. In addition, 4-Bit Ripple Carry Adder (4-DG-IndiM RCA) application circuit using the proposed DG-IndiMFA circuit is preferred and is investigated for design parameters at 16 nm at a supply voltage of 0.7 V. Enhanced results validate the physical layout design, as the proposed DG-IndiMFA circuit and proposed application 4-DG-IndiM RCA circuit occupy an optimized area of 20.6 µm2 and 90 µm2, respectively.