Posit arithmetic, known for its balanced trade-off between dynamic range and accuracy, has gained attention as a potential alternative to the IEEE 754 floating-point standard in deep learning applications. However, the hardware design for posit arithmetic, particularly for dot-product operations in deep neural networks (DNNs), remains underexplored. Current hardware implementations typically use either a combination of multipliers with adder trees or cascaded fused multiply–add (FMA) units, both of which result in inefficient computation and high resource consumption. To address this, the authors propose a posit dot-product unit (PDPU) designed for efficient and high-throughput hardware implementations. This PDPU adopts a fused and mixed-precision architecture, which reduces unnecessary hardware complexity and latency. It also features a fine-grained 6-staged pipeline, which enhances overall performance. Our new architecture replaces traditional designs that use compressors and carry-save adder (CSA) trees. The existing method’s recursive nature leads to increased power consumption and larger area requirements. By substituting these with a Ripple Carry Adder (RCA) and implementing conditional logic, our design eliminates the recursive bottleneck, significantly improving both power efficiency and area utilization. The proposed architecture is evaluated against traditional designs, demonstrating its superiority in terms of power and area savings.