In this work, we designed polynomial multipliers of various sizes (4, 8, 16, 32, 64, and 512 terms) for both Schoolbook and Optimized Karatsuba Multiplier algorithms. A comparison between the two multipliers demonstrates that the Karatsuba multiplier performs with superior efficiency and lower resource utilization. The 512 term Karatsuba multiplier using 32 term blocks, implemented in a loop, is integrated with NTRU Encrypt a post-quantum cryptography algorithm, where it outperforms in terms of performance achieving 42.89% reduction in LUT’s compared to the reference paper. The design enhances both the efficiency and resource utilization when integrated with NTRU Encrypt.

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Polynomial Multiplier Hardware Accelerator for Encryption Techniques

  • G Akshay Sharma,
  • Rohith Ravindra,
  • S. H. Shreyas,
  • T. Ananda Bagavathi,
  • B. Rajeshwari

摘要

In this work, we designed polynomial multipliers of various sizes (4, 8, 16, 32, 64, and 512 terms) for both Schoolbook and Optimized Karatsuba Multiplier algorithms. A comparison between the two multipliers demonstrates that the Karatsuba multiplier performs with superior efficiency and lower resource utilization. The 512 term Karatsuba multiplier using 32 term blocks, implemented in a loop, is integrated with NTRU Encrypt a post-quantum cryptography algorithm, where it outperforms in terms of performance achieving 42.89% reduction in LUT’s compared to the reference paper. The design enhances both the efficiency and resource utilization when integrated with NTRU Encrypt.