Modern AI accelerators face significant challenges in balancing memory bandwidth, capacity, and cost requirements, particularly for large model inference tasks. Traditional solutions often rely on expensive high-bandwidth memory or struggle with limited memory capacity and bandwidth utilization. This paper presents a novel AI accelerator architecture that effectively addresses these challenges through a DDR-based approach. Our design features a hybrid multi-channel DDR memory system with dynamic interleaving modes, coupled with a high-performance Controller CPU for sophisticated task scheduling. Through careful hardware-software co-design, our architecture achieves efficient utilization of both memory bandwidth and compute resources while maintaining programming simplicity. The memory system supports flexible data movement patterns and enables efficient handling of diverse AI workloads. The results of silicon implementation demonstrate high performance in memory bandwidth utilization, computational efficiency, and model inference tasks, validating the effectiveness of our approach in providing high memory bandwidth and large memory capacity. Our work establishes a practical paradigm for designing efficient AI accelerators using DDR-based memory systems.