CMOS technology is the leading-edge design method for emerging dynamic logic for charge-sharing circuits. Some reliable circuit-designing techniques and architectural modifications are needed to create charge-sharing-free dynamic logic gate circuits. This paper aims to study the charge-sharing occurrence and its outcomes for fiery logic gates. Design trade-offs and circuit-level enhancements are also considered to optimize while retaining adequate area utilization and performance. The footed dynamic 2-NAND logic, additional precharge circuit, and charge keeper circuit have all been studied for charge-sharing circuits. The proposed CMOS charge-sharing circuits offer enhanced flexibility, lower power consumption, and improved circuit speed.