In this paper, we investigate a dynamic comparator with high speed and sensitivity that makes optimal use of electricity. This kind of comparator can be employed in applications involving high-speed ADCs where sensitivity and speed are crucial considerations. For high speed, delay time of discharge path is reduced by reducing the overall parasitic latch resistance. Parallel clock input switches are added in the latch which significantly reduced the latch resistance and improves support for the differential amplifier stage to increases sensitivity. The proposed comparator’s delay and sensitivity are significantly better than those of the traditional dynamic latch comparator. The proposed comparator is not much complex in contrast to double-tail dynamic comparators which are also having delay time equivalent to this work. All the comparators design are simulated in 90 nm CMOS technology node in Cadence Virtuoso Tool. The suggested dynamic comparator has a delay time of 0.184 ns, a resolution of 30uV and a power consumption of 270.52uW at 0.5 GHz frequency and 1.2 V power supply.