It is too difficult to deal with square of any large signed number by conventional methods. Therefore, parallel and partial product while squaring of signed number is very complex and time-consuming. In this paper, we suggest a Very Large-Scale Integration (VLSI) design of an efficient signed square architecture using non-conventional method. The square of a large magnitude signed number is reduced to a lower magnitude signed multiplication and an addition operation by Yavadunam algorithm. The suggested method finds the deficit of the signed number from the adjacent base to perform the signed square operation. The proposed design is coded using Verilog Hardware Description Language. The synthesis and simulation of this architecture are performed using Xilinx ISE 14.7 software. Further this architecture is implemented on the Virtex-4 and Spartan 3 Field Programmable Gate Array (FPGA) device. The validation of the proposed architecture is examined using the performance parameters, such as path delay, and area. The synthesis results show delay-area complexity improvement over the state-of-the-art architectures. The superiority of the proposed architecture is claimed based on performance comparisons with the early square and multiplier architecture.