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In this article, we intend to design 6 T Static RAM (SRAM) using hybrid combination of Carbon Nanotube Field Effect Transistor (CNFET) and Fin-Field Effect Transistor (FinFET) for achieving lesser power and delay with improved device stability. The proposed work focuses on the power and delay analysis of SRAM circuits, while considering the intricate interplay between performance, energy efficiency, and reliability. At the end, we have integrated the circuit using both the technologies, i.e., CNFET and FinFET, and designed the improved and more reliable SRAM circuit. A typical CMOS technology confronts a number of hurdles and limits as the technological node in nanometers (nm) continues to decrease. However, the hybrid approach allows designers to optimize different aspects of the circuit based on the specific requirements and trade-offs. The results shed important light on the compromises and potential benefits of CMOS, CNFET, and FinFET implementations implemented in 20 nm technology. The hybrid SRAM design incorporating CNFET and FinFET provides an appealing option for users who expect low power consumption, improved delay, and stability.

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Low Power Static RAM: A Novel Hybrid Design and Implementation with CNFET and FinFET

  • 会议论文

  • 发表日期：

    2026年

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  • Krati Haldiya,
  • Nirmal Kumar Sharma,
  • G. Lakshmi Priya,
  • Lucky Agarwal

摘要

In this article, we intend to design 6 T Static RAM (SRAM) using hybrid combination of Carbon Nanotube Field Effect Transistor (CNFET) and Fin-Field Effect Transistor (FinFET) for achieving lesser power and delay with improved device stability. The proposed work focuses on the power and delay analysis of SRAM circuits, while considering the intricate interplay between performance, energy efficiency, and reliability. At the end, we have integrated the circuit using both the technologies, i.e., CNFET and FinFET, and designed the improved and more reliable SRAM circuit. A typical CMOS technology confronts a number of hurdles and limits as the technological node in nanometers (nm) continues to decrease. However, the hybrid approach allows designers to optimize different aspects of the circuit based on the specific requirements and trade-offs. The results shed important light on the compromises and potential benefits of CMOS, CNFET, and FinFET implementations implemented in 20 nm technology. The hybrid SRAM design incorporating CNFET and FinFET provides an appealing option for users who expect low power consumption, improved delay, and stability.