Analog CMOS Implementations of Hardware Neurons for Slow Electronics
摘要
To realize CMOS-based hardware spiking neural networks (SNNs), area- and power-efficient neuron circuits are essential. We propose a compact leaky integrate-and-fire (LIF) neuron circuit with a long and tunable time constant, which consists of a capacitor and two pseudo resistors (PRs). The fabricated LIF neuron has a power consumption of 6 \(\mu \) W and a leak time constant of up to 1.2 ms, which is tunable by changing the bias voltage of the PRs. We also propose a neural structure for generating and transmitting time-domain signals, including a neuron module, a synapse module, and two weight modules. The proposed neural structure is driven by a leakage current of MOS transistors and uses an inverter-based comparator to realize a firing function, thus providing higher energy and area efficiency compared to conventional designs. Simulation results of the spiking neural network for reservoir computing with the behavioral model of the proposed neural structure demonstrate the learning function.