This paper presents a memory-efficient architecture for the fast Fourier transform (FFT), aimed at significantly reducing memory consumption and multiplexer usage. This design is particularly effective for high-throughput and low-latency applications such as real-time signal processing, wireless communication, and radar systems. Using four parallel memory modules, each storing N/4 samples, the architecture allows simultaneous read and write operations across all modules, thus minimizing latency and enhancing throughput. The design employs a consistent permutation scheme based on the perfect shuffle method, eliminating the need for re-configuring shuffling circuits and simplifying the design. Additionally, uniform read and write addresses across all memory units streamline control and facilitate memory consolidation. The architecture has been effectively deployed on a field-programmable gate array (FPGA). The proposed architecture realizes a 29% reduction in the utilization of look-up tables, alongside a 10% diminution in power consumption. Demonstrating its practical viability in systems that require optimized resource management and high performance.